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revision 1.0 january 2005 K1B6416B6C - 1 - u t ram document title 4mx16 bit synchronous burst uni-transistor random access memory the attached datasheets are provided by samsu ng electronics. samsung electronics co., ltd. reserve the right to change the spe cifications and products. samsung electronics will answer to your questions about device. if you have any questio ns, please contact the samsung branch offices. revision history revision no. 0.0 0.1 0.2 0.3 0.4 1.0 remark advance advance advance preliminary preliminary final history initial draft - design target revised - deleted deep power down mode support revised - changed product code from k1b6416b7c into K1B6416B6C revised - filled out package type(54ball fbga 6.0mm x 8.0mm) - changed hi-z parameters(tchz, tohz, tbhz, twz) from max.7ns into max.12ns and changed thz from max.10ns into max.12ns - updated "fig.17 timing waveform of write cycle(1)" in page 23 - added comment on standby current(i sb1 ) measure condition as "standby mode is supposed to be set up after at least one active operation after power up. i sb1 is measured after 60ms from the time when standby mode is set up." - added comment on restriction of the transition between asynchro- nous write operation and fully synchronous bus operation(page 10,11) - filled out i sb1 value, i sbp value and i cc2 value in table 17(dc and operating characteristics) - added synchronous operating current(i cc3 , max.40ma) - added tcshp(a)(cs high pulse width) parameter as min.10ns in the asynchronous ac characteristics revised - changed i sb1 (< 40 c) and i sbp (3/4 block, < 40 c) from 100 a into 120 a - changed i sbp (1/2 block and 1/4 block, < 40 c) from 95 a into 115 a finalized draft date march 11, 2004 april 19, 2004 may 10, 2004 september 1, 2004 october 12, 2004 january 20, 2005
revision 1.0 january 2005 K1B6416B6C - 2 - u t ram 4m x 16 bit synchronous bu rst uni-transi stor cmos ram features ? process technology: cmos ? organization: 4m x16 bit ? power supply voltage: 1.7~2.0v ? three state outputs ? supports mrs (mode register set) ? mrs control - mrs pin control ? supports power saving modes - partial array refresh mode internal tcsr ? supports driver strength optimization for system environment power saving. ? supports asynchronous 4-page read and asynchronous write operation ? supports synchronous burst read and asynchronous write operation(address latch type and low adv type) ? supports synchronous burst read and synchronous burst write operation ? synchronous burst(read/write) operation - supports 4 word / 8 word / 16 word and full page(256 word) burst - supports linear burst type & interleave burst type - latency support : latency 5 @ 66mhz(tcd 10ns) latency 4 @ 54mhz(tcd 10ns) - supports burst read suspend in no clock toggling - supports burst write data masking by /ub & /lb pin control - supports wait pin function for indica ting data availability. ? max. burst clock frequency : 66mhz ? package type : 54 ball fbga 6.0mm x 8.0mm samsung electronics co., ltd. reserves the right to change produc ts and specifications without notice . general description the world is moving into the mobile multi-media era and there- fore the mobile handsets need much bigger memory capacity to handle the multi-media data. samsung?s utram products are designed to meet all the request from the various customers who want to cope with the fast growing mobile market. utram is the perfect solution for the mobile market with its low cost, high density and high performance feature. K1B6416B6C is fabricated by samsung s advanced cmos technology using one transistor memory cell. the device supports the traditi onal sram like asynchronous bus operation(asynchronous page read and asynchronous write), the nor flash like sy nchronous bus operation(synchro- nous burst read and asynchronous write) and the fully synchro- nous bus operation(synchronous burst read and synchronous burst write). these three bus operation modes are defined through the mode register setting. the device also supports the s pecial features for the standby power saving. those are the partial array refresh(par) mode and internal temperature compensated self refresh(tcsr) mode. the optimization of output driver strength is possible through the mode register setting to adjust for the different data loadings. through this driver strength optim ization, the device can mini- mize the noise generated on the data bus during read operation. table 1. product family product family operating temp. vcc range clock freq.(max) async. speed(taa) current consumption standby(max) (i sb1 , <40 c) standby(max) (i sb1 , <85 c) operating (i cc2 , i cc3 , max.) K1B6416B6C-i industrial(-40~85 c) 1.7~2.0v 66mhz 70ns 120 a 180 a 40ma
revision 1.0 january 2005 K1B6416B6C - 3 - u t ram fig.1 pin description name function name function clk clock input i/o 0 ~i/o 15 data inputs/outputs adv address input valid v cc /v ccq power supply mrs mode register set vss/v ssq ground cs chip select ub upper byte(i/o 8 ~ 15 ) oe output enable input lb lower byte(i/o 0 ~ 7 ) we write enable input wait data availability a 0 ~a 21 address inputs nc not connected table 2. pin description 54-fbga: top view(ball down) lb oe a0 a1 a2 mrs i/o8 ub a3 a4 cs i/o0 i/o9 i/o10 a5 a6 i/o1 i/o2 v ssq i/o11 a17 a7 i/o3 vcc v ccq i/o12 a21 a16 i/o4 vss i/o14 i/o13 a14 a15 i/o5 i/o6 i/o15 a19 a12 a13 we i/o7 a18 a8 a9 a10 a11 a20 1 23456 a b c d e f g h wait clk adv nc nc nc j
revision 1.0 january 2005 K1B6416B6C - 4 - u t ram contents revision history features and general description pin description power up sequence functional description mode register setting operation mode register setting timing asynchronous operation asynchronous 4 page read operation asynchronous write operation asynchronous write operation in synchronous mode synchronous burst operation synchronous burst read operation synchronous burst write operation synchronous burst operat ion terminology clock latency count burst length burst stop wait control burst type low power features internal tcsr driver strength optimization partial array refresh(par) mode product list absolute maximum ratings recommended dc operating conditions capacitance dc and operating characteristics asynchronous ac characteristics asynchronous timing waveforms synchronous ac characteristics synchronous timing waveforms transition timing waveforms package dimension 1 2 3 8 9 11 12 13 13 13 13 13 13 13 1 4 14 14 14 14 15 15 17 17 17 17 18 18 18 19 18 20 21 30 31 40 46 page
revision 1.0 january 2005 K1B6416B6C - 5 - u t ram list of tables table 1. product family table 2. pin description table 3. asynchronous 4 page read & asynchronous write mode truth table table 4. synchronous burst read & asynchronous write mode truth table table 5. synchronous burst read & sy nchronous burst write mode truth table table 6. mode register setti ng according to field of function table 7. mode register set table 8. mrs ac characteristics table 9. latency count support table 10. number of clocks for 1st data table 11. burst sequence table 12. par mode characteristics table 13. product list table 14. absolute maximum ratings table 15. recommended dc operating conditions table 16. capacitance table 17. dc and operating characteristics table 18. asynchronous ac characteristics table 19. asynchronous read ac characteristics table 20. asynchronous page read ac characteristics table 21. asynchronous write ac characteristics(we controlled) table 22. asynchronous write ac characteristics(ub & lb controlled) table 23. asynch. write in synch. mode ac characteristics(address latch type, we controlled) table 24. asynch. write in synch. mode ac characteristics(address latch type, ub & lb controlled) table 25. asynch. write in synch. mode ac characteristics(low adv type, we controlled) table 26. asynch. write in synch. mode ac characteristics(low adv type, ub & lb controlled) table 27. asynch. write in synch. mode ac characteristics(low adv type multiple write, we controlled) table 28. synchronous ac characteristics table 29. burst operation ac characteristics table 30. burst read ac characteristics(cs toggling consecutive burst) table 31. burst read ac characteristics(cs low holding consecutive burst) table 32. burst read ac characteristics(last data sustaining) table 33. burst write ac characteristics(cs toggling consecutive burst) table 34. burst write ac characteristics(cs low holding consecutive burst) table 35. burst read stop ac characteristics table 36. burst write stop ac characteristics table 37. burst read suspend ac characteristics table 38. burst read to asynch. write( address latch type) ac characteristics table 39. burst read to asynch. write(low adv type) ac characteristics table 40. asynch. write(address latch type) to burst read ac characteristics table 41. asynch. write(low adv type) to burst read ac characteristics table 42. burst read to burst write ac characteristics table 43. burst write to burst read ac characteristics 2 3 9 9 10 11 11 12 14 14 16 17 18 18 18 19 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 page
revision 1.0 january 2005 K1B6416B6C - 6 - u t ram list of figures figure 1. pin description figure 2. functional block diagram figure 3. power up timing figure 4. standby mode state machine figure 5. mode register setting timing figure 6. asynchronous 4-page read figure 7. asynchronous write figure 8. synchronous burst read figure 9. synchronous burst write figure 10. latency configuration(read) figure 11. wait control and read/write latency control figure 13. par mode execution and exit figure 14. ac output load circuit(asynchronous) figure 15. timing waveform of asynchronous read cycle figure 16. timing waveform of page read cycle figure 17. timing waveform of write cycle(asynchronous, we controlled) figure 18. timing waveform of write cycle(asynchronous, ub & lb controlled) figure 19. timing waveform of write cycle(asynchronous, address latch type, we controlled) figure 20. timing waveform of write cycle(asynchronous, address latch type, ub & lb controlled) figure 21. timing waveform of write cycle(asynchronous, low adv type, we controlled) figure 22. timing waveform of write cycle(asynchronous, low adv type, ub & lb controlled) figure 23. timing waveform of multiple write cycle(asynchronous, low adv type, we controlled ) figure 24. ac output load circuit(synchronous) figure 25. timing waveform of basic burst operation figure 26. timing waveform of burst read cycle(cs toggling consecutive burst read) figure 27. timing waveform of burst read cycle(cs low holding consecutive burst read) figure 28. timing waveform of burst read cycle(last data sustaining) figure 29. timing waveform of burst write cycle(cs toggling consecutive burst write) figure 30. timing waveform of burst write cycle(cs low holding consecutive burst write) figure 31. timing waveform of burst read stop by cs figure 32. timing waveform of burst write stop by cs figure 33. timing waveform of burst read suspend cycle figure 34. synch. burst read to asynch. write(address latch type) timing waveform figure 35. synch. burst read to asynch. write(low adv type) timing waveform figure 36. asynch. write(address latch type) to synch. burst read timing waveform figure 37. asynch. write(low adv type) to synch. burst read timing waveform figure 38. synch. burst read to synch. burst write timing waveform figure 39. synch. burst write to synch. burst read timing waveform 3 7 8 8 12 13 13 13 13 14 15 17 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 page
revision 1.0 january 2005 K1B6416B6C - 7 - u t ram fig.2 functional block diagram clk generator row select i/o 0 ~i/o 7 data controller i/o 8 ~i/o 15 vcc vss precharge circuit. memory array i/o circuit column select oe cs we adv ub control logic mrs row addresses column addresses lb clk wait data controller data controller
revision 1.0 january 2005 K1B6416B6C - 8 - u t ram power up sequence after applying v cc upto minimum operating voltage(1.7v), drive cs high first and then drive mrs high. then the device gets into the power up mode. wait for minimum 200 s to get into the normal operation mode. during the power up mode, the standby current can not be guaranteed. to get the stable standby current level, at least one cycle of active oper ation should be implemented regard less of wait time duration. to get the appropriate device oper ation, be sure to keep the following power up sequence. 1. apply power. 2. maintain stable power(vcc min.=1.7v) for a minimum 200 s with cs and mrs high. 200 s ~ ~ v cc fig.3 power up timing v cc(min) min. 200 s mrs cs normal operation min. 0ns power up mode (note) 1. after v cc reaches v cc (min.), wait 200 s with cs and mrs high. then the device gets into the normal operation. min. 0ns fig.4 standby mode state machines default mode after power up is asynchronous mode(4 page read an d asynchronous write). but this default mode is not 100% guaranteed so mrs setting sequence is highly recommended after power up. for entry to par mode, drive mrs pin into v il for over 0.5 s(suspend period) during standby mode after mrs setting has been completed(a4=1, a3=0). if mrs pin is driven into v ih during par mode, the device gets back to the standby mode without wake up sequence. cs =v ih cs =v il , ub or lb =v il mrs =v ih power on initial state (wait 200 s) active standby mode cs =v ih par mode mrs setting cs =ub =lb =v il , we =v il , mrs =v il mrs =v ih mrs setting cs =v il , we =v il , mrs =v il mrs =v ih mrs =v il
revision 1.0 january 2005 K1B6416B6C - 9 - u t ram table 4. synchronous burst read & asynchro nous write mode(a15/a14=0/1) 1. x must be low or high state. 2. x means "don?t care"(can be low, high or toggling). 3. /wait is device output signal so does not have any affect to the mode definition. please refer to each timing diagram for /w ait pin function. cs mrs oe we lb ub i/o 0~7 i/o 8~15 clk adv mode power hh x 1) x 1) x 1) x 1) high-z high-z x 2) x 2) deselected standby hl x 1) x 1) x 1) x 1) high-z high-z x 2) x 2) deselected par lhhh x 1) x 1) high-z high-z x 2) h output disabled active lh x 1) x 1) h h high-z high-z x 2) h output disabled active lh x 1) h x 1) x 1) high-z high-z read command active l h l h l h dout high-z h lower byte read active l h l h h l high-z dout h upper byte read active l h l h l l dout dout h word read active l h h l l h din high-z x 2) o r l o w e r b y t e w r i t e a c t i v e l h h l h l high-z din x 2) or upper byte write active lhhllldin din x 2) or word write active l l h l l l high-z high-z x 2) or mode register set active table 3. asynchronous 4 page read & asy nchronous write mode(a15/a14=0/0) 1. x must be low or high state. 2. in asynchronous mode, clock and adv are ignored. 3. /wait pin is high-z in asynchronous mode. cs mrs oe we lb ub i/o 0~7 i/o 8~15 mode power hh x 1) x 1) x 1) x 1) high-z high-z deselected standby hl x 1) x 1) x 1) x 1) high-z high-z deselected par lhhh x 1) x 1) high-z high-z output disabled active lh x 1) x 1) h h high-z high-z output disabled active l h l h l h dout high-z lower byte read active l h l h h l high-z dout upper byte read active l h l h l l dout dout word read active l h h l l h din high-z lower byte write active l h h l h l high-z din upper byte write active l h h l l l din din word write active l l h l l l high-z high-z mode register set active functional description
revision 1.0 january 2005 K1B6416B6C - 10 - u t ram table 5. synchronous burst read & synchrono us burst write mode(a15/a14=1/0) 1. x must be low or high state. 2. x means "don?t care"(can be low, high or toggling). 3. /wait is device output signal so does not have any affect to the mode definition. please refer to each timing diagram for /w ait pin function. 4. the last data written in the previous asynchronous write mode is not valid. to make the lastly written data valid, then impl ement at least one dummy write cycle before change mode into synchronous burst read and synchronous burst write mode. 5. the data written in synchronous burst write operation can be corrupted by the next asynchronous write operation. so the tran sition from synchronous burst write operation to asynchronous write operation is prohibited. cs mrs oe we lb ub i/o 0~7 i/o 8~15 clk adv mode power hh x 1) x 1) x 1) x 1) high-z high-z x 2) x 2) deselected standby hl x 1) x 1) x 1) x 1) high-z high-z x 2) x 2) deselected par lhhh x 1) x 1) high-z high-z x 2) h output disabled active lh x 1) x 1) h h high-z high-z x 2) h output disabled active lh x 1) h x 1) x 1) high-z high-z read command active l h l h l h dout high-z h lower byte read active l h l h h l high-z dout h upper byte read active l h l h l l dout dout h word read active lh x 1) l or x 1) x 1) high-z high-z write command active lhh x 1) l h din high-z h lower byte write active lhh x 1) h l high-z din h upper byte write active lhh x 1) l l din din h word write active l l h l or l l high-z high-z mode register set active
revision 1.0 january 2005 K1B6416B6C - 11 - u t ram mode register setting operation the device has several modes : asynchronous page read m ode, asynchronous write mode, synchronous burst read mode, syn- chronous burst write mode, standby mode and partial array refresh(par) mode. partial array refresh(par) mode is defined through mode register set(mrs) option. mode register set(mrs) option also defines burst length, burst type, wait polarity and latency count at synchronous burst read/write mode. mode register set (mrs) the mode register stores the data for controlling the various oper ation modes of utram. it programs partial array refresh(par), burst length, burst type, latency count and vari ous vendor specific options to make utra m useful for a variety of different app lica- tions. the default values of mode register are defined, ther efore when the reserved address is input, the device runs at defaul t modes. the mode register is written by driving cs , adv , we , ub , lb and mrs to v il and driving oe to v ih during valid address. the mode register is divided into various fields depending on the fields of functions. the partia l array refresh(par) field uses a0~a4, burst length field uses a5~a7, burst type uses a8, latency count uses a9 ~a11, wait polarity uses a13, operation mode uses a14~a15 and driver strength uses a16~a17. refer to the table below for detailed mode register setting . a18~a21 addresses are "don?t care" in mode register setting. table 6. mode register setting according to field of function note : ds(driver strength), ms(mode select), wp(wai t polarity), latency(latency count), bt(burst type), bl(burst length), par(partial array refresh), para(partial array refresh array), pars(partial array refresh size), rfu(reserved for future use) table 7. mode register set note : the address bits other than those listed in the table above are reserved. for example, burst length address bits(a7:a6:a5) have 4 sets of reserved bits like 0:0:0, 0:0:1, 1:0:1 and 1:1:0. if the reserved address bits are input, then t he mode will be set into the default mode. each field has its own d efault mode and these default modes are written in blue-bold in the table above. but this default mode is not 100% guaran teed so mrs setting sequence is highly recommended after power up. a12 is a reserved bit for future use. a12 must be set as "0". not all the mode settings are tested. per the mode settings to be tested, plea se contact samsung product planning team. 256 word full page burst mode needs to meet tbc(burst cycle time) parameter as max. 2500ns . * the last data written in the previous asyn chronous write mode is not valid. to make the lastly written data vali d, then imple- ment at least one dummy write cycle befor e change mode into synchronous burst read and synchronous burst write m ode. * the data written in synchronous burst write operation can be corrupted by the next asynchronous write operation. so the transition from synchronous burst write operation to asynchronous write operation is prohibited. address a17~a16 a15~a14 a13 a12 a11~a9 a8 a7~a5 a4~a3 a2 a1~a0 function ds ms wp rfu latency bt bl par para pars driver strength mode select a17 a16 ds a15 a14 ms* 00 full drive 00 async. 4 page read / async. write 0 1 1/2 drive 0 1 sync. burst read / async. write 1 0 1/4 drive 1 0 sync. burst read / sync. burst write wait polarity rfu latency count burst type burst length a13 wp a12 rfu a11 a10 a9 latency a8 bt a7 a6 a5 bl 0 low enable 0 must 000 3 0 linear 01 0 4 word 1 high enable 1 - 0 0 1 4 1 interleave 0 1 1 8 word 010 5 10 0 16 word 0 1 1 6 1 1 1 full(256 word) partial array refresh par array par size a4 a3 par a2 para a1 a0 pars 1 0 par enable 0 bottom array 00 full array 11 par disable 1 top array 0 1 3/4 array 1 0 1/2 array 1 1 1/4 array
revision 1.0 january 2005 K1B6416B6C - 12 - u t ram mrs pin control type mode register setting timing in this device(K1B6416B6C), mrs pin is used for two purposes. one is to get into the mode register setting and the other one is to execute partial array refresh mode. to get into the mode register sett ing, the system must drive mrs pin to v il and immediately(within 0.5 s) issue a write com- mand(drive cs , adv , ub , lb and we to v il and drive oe to v ih during valid address). if the subsequent write command(we signal input) is not issued within 0.5 s, then the device might get into the par mode. fig.5 mode register setting timing (oe =v ih ) register update complete t wu address ub , lb we t wc t cw t aw t bw t wp t as cs t mw register write start register write complete adv mrs 12345678910111213 clk 0 (mrs setting timing) 1. clock input is ignored. table 8. mrs ac characteristics (v cc =1.7~2.0v, t a =-40 to 85 c, maximum main clock frequency=66mhz) parameter list symbol speed units min max mrs mrs enable to register write start t mw 0 500 ns end of write to mrs disable t wu 0-ns
revision 1.0 january 2005 K1B6416B6C - 13 - u t ram asynchronous operation asynchronous 4 page read operation asynchronous normal read operation starts when cs , oe and ub or lb are driven to v il under the valid address without tog- gling page addresses(a0, a1). if the page addresses(a0, a1) are toggled under the other valid address, the first data will be out with the normal read cycle time(trc) and the second, the third and the fourth data will be out with the page cycle time(tpc). (mrs and we should be driven to v ih during the asynchronous (page) read operation) clock, adv , wait signals are ignored during the asynchronous (page) read operation. asynchronous write operation asynchronous write operation starts when cs , we and ub or lb are driven to v il under the valid address.(mrs and oe should be driven to v ih during the asynchronous write opera- tion.) clock, adv , wait signals are ignored during the asyn- chronous (page) read operation. asynchronous write operation in syn- chronous mode a write operation starts when cs , we and ub or lb are driven to v il under the valid address. clock input does not have any affect to the write operation(mrs and oe should be driven to v ih during write operation. adv can be either toggling for address latch or held in v il ). clock, adv , wait signals are ignored during the asynchronous (page) read operation. synchronous burst operation burst mode operations enable the system to get high perfor- mance read and write operation. the address to be accessed is latched on the rising edge of clock or adv (whichever occurs first). cs should be setup before the address latch. during this first clock rising edge, we indicates whether the operation is going to be a read(we high) or a write(we low). for the optimized burst mode to each system, the system should determine how many clock cycles are required for the first data of each burst access(latency count), how many words the device outputs at an access(burst length) and which type of burst operation(burst type : linear or interleave) is needed. the wait polarity should also be determined.(see table "mode register set") synchronous burst read operation the synchronous burst read command is implemented when the clock rising is detected during the adv low pulse. adv and cs should be set up before the clock rising. during read com- mand, we should be held in v ih . the multiple clock risings(dur- ing low adv period) are allowed but the burst operation starts from the first clock rising. the fi rst data will be out with latency count and tcd. synchronous burst write operation the synchronous burst write command is implemented when the clock rising is detected during the adv and we low pulse. adv , we and cs should be set up before the clock rising. the multiple clock risings(during low adv period) are allowed but the burst operation starts from the first clock rising. the first data will be written in the latency clock with tds. a21~a2 a1~a0 cs ub , lb oe data out high-z high-z high-z address cs ub , lb we data in data out fig.6 asynchronous 4-page read fig.7 asynchronous write clk adv addr. ub , lb oe data out cs wait 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 fig.8 synchronous burst read (latency 5, bl 4, wp : low enable) fig.9 synchronous burst write (latency 5, bl 4, wp : low enable) clk adv addr. ub , lb we data in cs wait 0 1 2 3 4 5 6 7 8 9 10 11 12 13
revision 1.0 january 2005 K1B6416B6C - 14 - u t ram address data out adv clock dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 data out dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 data out dq1 dq2 dq3 dq4 dq5 dq6 dq7 data out dq1 dq2 dq3 dq4 dq5 dq6 latency 3 latency 4 latency 5 latency 6 t synchronous burst o peration terminology clock(clk) the clock input is used as the reference for synchronous burst read and write operatio n of utram. the synchronous burst read an d write operation is synchronized to the rising edge of t he clock. the clock transitions must swing between v il and v ih . latency count the latency count configuration tells the dev ice how many clocks must elapse from the burst command before the first data shoul d be available on its data pins. this value depends on the input clock frequency. the supported latency count is as follows. table 9. latency count support : 3, 4, 5 table 10. number of clocks for 1st data fig.10 latency configuration(read) note : the first data will always keep the latency. from the second data, some per iod of wait time might be caused by wait pin. burst length burst length identifies how many data the device outputs at an a ccess. the device supports 4 word, 8 word, 16 word and 256 word burst read or write. 256 word full page burst mode needs to meet tbc(burst cycle time) parameter as max. 2500ns. the first data will be out with the set latency + tcd. from the second data, the data will be out with tcd from each clock. burst stop burst stop is used when the system wants to stop bur st operation on special purpose. if driving cs to v ih during the burst read opera- tion, then the burst operation will be stopped. during the burst read operation, the new burst operation can not be issued. the new burst operation can be issued only after the previous burst operation is finished. the burst stop feature is very useful becaus e it enables the user to utilize the un-supported burst length such as 1 burst or 2 burst which accounts for big portion in usage for the mobile handset application environment. clock frequency upto 66mhz upto 54mhz upto 40mhz latency count 5 4 3 set latency latency 3 latency 4 latency 5 # of clocks for 1st data(read) 4 5 6 # of clocks for 1st data(write) 2 3 4
revision 1.0 january 2005 K1B6416B6C - 15 - u t ram synchronous burst operation terminology wait control(wait ) the wait signal is the device?s output signal whic h indicates to the host system when the device?s data-out or data-in is valid. to be compatible with the flash interfaces of various microprocessor types, the wait polarity(wp) can be configured. the polarity can be programmed to be either low enable or high enable. for the timing of wait signal, the wait signal should be set active one clock prior to the data regardless of read or write cycle. burst type the device supports linear type burst sequenc e and interleave type burst sequence. linear type burst sequentially increments th e burst address from the starting address. t he detailed linear and interleave type burst add ress sequence is shown in burst seque nce table in next page. 12345678910111213 adv read clk dq0 dq1 0 dq2 fig.11 wait control and read/write latency control(late ncy : 5, burst length : 4, wp : low enable) write d0 d1 d2 dq3 d3 data out data in cs latency 5 latency 5 high-z wait high-z wait
revision 1.0 january 2005 K1B6416B6C - 16 - u t ram table 11. burst sequence 1. wrap : burst address wraps within word boundar y and ends after fulfilled the burst length. 2. 256 word full page burst mode needs to meet tb c(burst cycle time) parameter as max. 2500ns. start addr. burst address sequence(decimal) wrap 1) 4 word burst 8 word burst 16 word burst full page(256 word) linear interleave linear interleave linear interleave linear 0 0-1-2-3 0-1-2-3 0-1-...-5-6-7 0-1 -2-...-6-7 0-1-2-...-14-15 0-1- 2-3-4...14-15 0-1-2-...-254-255 1 1-2-3-0 1-0-3-2 1-2-...-6-7-0 1 -0-3-...-7-6 1-2-3-...-15-0 1-0-3-2-5...15-14 1-2-3-...-255-0 2 2-3-0-1 2-3-0-1 2-3-...-7-0-1 2 -3-0-...-4-5 2-3-4-...-0-1 2-3 -0-1-6...12-13 2-3-4-...-255-0-1 3 3-0-1-2 3-2-1-0 3-4-...-0-1-2 3-2-1-...-5-4 3-4-5 -...-1-2 3-2-1-0-7...13-12 3-4-5-...-255-0-1-2 4 4-5-...-1-2-3 4-5-6-...-2-3 4-5-6-...-2- 3 4-5-6-7-0...10-11 4-5-6-...-255-0-1-2-3 5 5-6-...-2-3-4 5-4-7-...-3-2 5-6-7-...-3- 4 5-4-7-6-1...11-10 5-6-7-...-255-...-3-4 6 6-7-...-3-4-5 6-7-4-...-0-1 6-7-8-...-4- 5 6-7-4-5-2...8-9 6-7-8-...-255-...-4-5 7 7-0-...-4-5-6 7-6-5-...-1-0 7-8-9-...-5- 6 7-6-5-4-3...9-8 7-8-9-...-255-...-5-6 ~ ~~ ~ 14 14-15-0-...-12-13 14-15-12-...- 0-1 14-15-...-255-...-12-13 15 15-0-1-...-13-14 15-14-13-...- 1-0 15-16-...-255-...-13-14 ~ ~ 255 255-0-1-...-253-254
revision 1.0 january 2005 K1B6416B6C - 17 - u t ram low power features partial array refresh(par) mode the par mode enables the user to specify the active memory array size. utram consists of 4 blocks and user can select 1 block, 2 blocks, 3 bl ocks or all blocks as active memory array through mode register setting. the active memory array is periodically refreshed whereas t he disabled array is not going to be refreshed and so the previously stored data will get lost. even though par mode is enabled through the mode register setting, par mode execution by mrs pin is still needed. the normal operation can be exec uted even in refresh-disabled array as long as mrs pin is not driven to low for over 0.5 s. driving mrs pin to high makes the device to get back to the normal operation mode from par executed mode, refer to fig.13 and table 12 for par operation and par address mapping. driver strength optimization the optimization of output driver strength is possible through the mode register setting to adjust for the different data load- ings. through this driver strengt h optimization, the device can minimize the noise generated on the data bus during read oper- ation. the device supports full drive, 1/2 drive and 1/4 drive. internal tcsr the internal temperature compensated self refresh(tcsr) feature is a very useful tool for reducing standby current in room temperature(below 40 c). dram cell has weak refresh charac- teristics in higher temperature. so high temperature requires more refresh cycles, which lead to standby current increase. without internal tcsr, the refresh cycle should be set as worst condition so as to cover high temperature(85 c) refresh char- acteristics. but with internal tcsr, the refresh cycle below 40 c can be optimized, so the standby current in room temper- ature can be highly reduced. this feature is really beneficial to mobile phone because most of mobile phones are used at below 40 c in the phone standby mode. fig.13 par mode execution and exit mrs mode cs normal operation suspend normal operation par mode 0.5 s table 12. par mode characteristic 1. only the data in the refreshed block are valid 2. par array can be selected through mode register set(see page 11) 3. standby mode is supposed to be set up after at least one active operation.after power up. i sb1 is measured after 60ms from the time when standby mode is set up. power mode address (bottom array) 2) address (top array) 2) memory cell data standby 3) (i sb1 , <40 c) standby 3) (i sb1 , <85 c) wait time( s) standby(full array) 000000h ~ 3fffffh 000000h ~ 3fffffh valid 1) 120 a 180 a0 partial refresh(3/4 block) 000000h ~ 2fffffh 100000h ~ 3fffffh valid 1) 120 a 180 a0 partial refresh(1/2 block) 000000h ~ 1fffffh 200000h ~ 3fffffh valid 1) 115 a 165 a0 partial refresh(1/4 block) 000000h ~ 0fffffh 300000h ~ 3fffffh valid 1) 115 a 165 a0
revision 1.0 january 2005 K1B6416B6C - 18 - u t ram table 13. product list industrial temperature products(-40~85 c) part name function K1B6416B6C 1.8v, 70ns, 66mhz table 14. absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ra tings" may cause permanent damage to the device. functional ope ration should be restricted to be used under recommended operating condition. expo sure to absolute maximum rating conditions longer than 1 secon d may affect reli- ability. item symbol ratings unit voltage on any pin relative to vss v in , v out -0.2 to v cc +0.3v v power supply voltage relative to vss v cc -0.2 to 2.5v v power dissipation p d 1.0 w storage temperature t stg -65 to 150 c operating temperature t a -40 to 85 c table 15. recommended dc operating conditions 1) 1. t a =-40 to 85 c, otherwise specified. 2. overshoot: v cc +1.0v in case of pulse width 20ns. 3. undershoot: -1.0v in case of pulse width 20ns. 4. overshoot and undershoot are sampled, not 100% tested. item symbol min typ max unit power supply voltage v cc 1.7 1.85 2.0 v ground vss 0 0 0 v input high voltage v ih 0.8 x v cc - v cc +0.2 2) v input low voltage v il -0.2 3) -0.4v
revision 1.0 january 2005 K1B6416B6C - 19 - u t ram table 16. capacitance 1) (f=1mhz, t a =25 c) 1. capacitance is sampled, not 100% tested. item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf table 17. dc and operating characteristics 1. full array partial refresh current( i sbp ) is same as standby current( i sb1 ). 2. standby mode is supposed to be set up after at least one active operation.after power up. i sb1 is measured after 60ms from the time when standby mode is set up. item symbol test conditions min typ max unit input leakage current i li v in =vss to v ccq -1 - 1 a output leakage current i lo cs =v ih, mrs =v ih , oe =v ih or we =v il , v io =vss to v ccq -1 - 1 a average operating current(async) i cc2 cycle time=t rc +3t pc , i io =0ma, 100% duty, cs =v il , mrs =v ih, v in =v il or v ih --40ma average operating current(sync) i cc3 burst length 4, latency 5, 66mhz, i io =0ma, address transi- tion 1 time, cs =v il , mrs =v ih, v in =v il or v ih --40ma output low voltage v ol i ol =0.1ma - - 0.2 v output high voltage v oh i oh =-0.1ma 1.4 - - v standby current(cmos) i sb1 2) cs v ccq -0.2v, mrs v ccq -0.2v, other inputs=vss to v ccq < 40 c--120 a < 85 c--180 a partial refresh current i sbp 1) mrs 0.2v, cs v ccq -0.2v other inputs=vss to v ccq < 40 c 3/4 block - - 120 a 1/2 block - - 115 1/4 block - - 115 < 85 c 3/4 block - - 180 a 1/2 block - - 165 1/4 block - - 165
revision 1.0 january 2005 K1B6416B6C - 20 - u t ram ac operating conditions test conditions (test load and test input/output reference) input pulse level: 0.2 to v cc -0.2v input rising and falling time: 3ns input and output reference voltage: 0.5 x v cc output load: c l =30pf table 18. asynchronous ac characteristics (v cc =1.7~2.0v, t a =-40 to 85 c) 1. t wp (min)=70ns for continuous write operation over 50 times. parameter list symbol speed units min max common cs high pulse width t cshp(a) 10 - ns async. (page) read read cycle time t rc 70 - ns page read cycle time t pc 25 - ns address access time t aa -70ns page access time t pa -20ns chip select to output t co -70ns output enable to valid output t oe -35ns ub , lb access time t ba -35ns chip select to low-z output t lz 10 - ns ub , lb enable to low-z output t blz 5-ns output enable to low-z output t olz 5-ns chip disable to high-z output t chz 012ns ub , lb disable to high-z output t bhz 012ns output disable to high-z output t ohz 012ns output hold t oh 3-ns async. write write cycle time t wc 70 - ns chip select to end of write t cw 60 - ns adv minimum low pulse width t adv 7-ns address set-up time to beginning of write t as 0-ns address set-up time to adv falling t as(a) 0-ns address hold time from adv rising t ah(a) 7-ns cs setup time to adv rising t css(a) 10 - ns address valid to end of write t aw 60 - ns ub , lb valid to end of write t bw 60 - ns write pulse width t wp 55 1) -ns we high pulse width t whp 5 ns latency-1 clock - write recovery time t wr 0-ns we low to read latency t wlrl 1-clock data to write time overlap t dw 30 - ns data hold from write time t dh 0-ns figure 14. ac output load circuit vtt=0.5 x vcc 50 ? dout 30pf z0=50 ?
revision 1.0 january 2005 K1B6416B6C - 21 - u t ram asynchronous read timing waveform (asynchronous read cycle) 1. t chz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage leve ls. 2. at any given temperature and voltage condition, t chz (max.) is less than t lz (min.) both for a given devic e and from device to device interconnection. 3. in asynchronous read cycle, clock, adv and wait signals are ignored. fig.15 timing waveform of asynchronous read cycle (mrs =v ih, we =v ih , wait =high-z) data valid high-z t rc t oh t aa t ba t oe t olz t blz t lz t ohz t bhz t chz t co address cs ub , lb oe data out table 19. asynchronous read ac characteristics symbol speed units symbol speed units min max min max t rc 70 - ns t olz 5-ns t aa -70nst blz 5-ns t co -70nst lz 10 - ns t ba -35nst chz 012ns t oe -35nst bhz 012ns t oh 3-nst ohz 012ns t cshp(a) 10 - ns t cshp(a)
revision 1.0 january 2005 K1B6416B6C - 22 - u t ram (asynchronous 4 page read cycle) 1. t chz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage leve ls. 2. at any given temperature and voltage condition, t chz (max.) is less than t lz (min.) both for a given devic e and from device to device interconnection. 3. in asynchronous 4 page read cycle, clock, adv and wait signals are ignored. fig.16 timing waveform of page read cycle (mrs =v ih, we =v ih , wait =high-z) data valid data valid data valid data valid valid address valid address valid address valid address valid address t pc t pa a21~a2 a1~a0 cs oe t ohz t oe t co t aa data out t chz t oh ub , lb t bhz t ba t olz t blz high z t lz t rc asynchronous read timing waveform table 20. asynchronous page read ac characteristics symbol speed units symbol speed units min max min max t rc 70 - ns t oh 3-ns t aa -70nst olz 5-ns t pc 25 - ns t blz 5-ns t pa -20nst lz 10 - ns t co -70nst chz 012ns t ba -35nst bhz 012ns t oe -35nst ohz 012ns
revision 1.0 january 2005 K1B6416B6C - 23 - u t ram asynchronous write timing waveform table 21. asynchronous write ac characteristics (we controlled) 1. t wp (min)=70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t wc 70 - ns t as 0-ns t cw 60 - ns t wr 0-ns t aw 60 - ns t dw 30 - ns t bw 60 - ns t dh 0-ns t wp 55 1) -nst cshp(a) 10 - ns address data valid ub , lb we data in t wc t cw t bw t wp t dh t dw t wr t aw t as cs data out high-z high-z t wc t as t wr data valid t dh t dw t whp t wp t cw t aw t bw fig.17 timing waveform of write cycle(1) (mrs =v ih, oe =v ih , wait =high-z, we controlled) (asynchronous write cycle - we controlled) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest transition when cs goes high or we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs or we going high. 5. in asynchronous write cycle, clock, adv and wait signals are ignored. 6. condition for continuous write operation over 50 times : t wp (min)=70ns t cshp(a)
revision 1.0 january 2005 K1B6416B6C - 24 - u t ram address data valid ub , lb we data in data out high-z high-z t wc t cw t bw t wp t dh t dw t wr t aw t as cs fig.18 timing waveform of write cycle(2) (mrs =v ih, oe =v ih , wait =high-z, ub & lb controlled) (asynchronous write cycle - ub & lb controlled) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest transition when cs goes high or we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs or we going high. 5. in asynchronous write cycle, clock, adv and wait signals are ignored. asynchronous write timing waveform table 22. asynchronous write ac characteristics (ub & lb controlled) 1. t wp (min)=70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t wc 70 - ns t as 0-ns t cw 60 - ns t wr 0-ns t aw 60 - ns t dw 30 - ns t bw 60 - ns t dh 0-ns t wp 55 1) -ns
revision 1.0 january 2005 K1B6416B6C - 25 - u t ram fig.19 timing waveform of write cycle(address latch type) (mrs =v ih, oe =v ih , wait =high-z, we controlled) ub , lb we data in t bw t wp t dh t dw data valid (address latch type asynchronous write cycle - we controlled) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for word operation. a write ends at the earliest transition when cs goes high or we goes high. the t wp is measured from the beginning of write to the end of write. 2. t aw is measured from the address valid to the end of write. in this address latch type write timing, t wc is same as t aw. 3. t cw is measured from the cs going low to the end of write. 4. t bw is measured from the ub and lb going low to the end of write. 5. clock input does not have any affect to the write operation if the parameter twlrl is met. asynchronous write timing waveform in synchronous mode adv address cs valid t as(a) t ah(a) t css(a) t cw data out high-z 12345678910111213 clk 0 t as read latency 5 high-z t wlrl 14 t aw table 23. asynch. write in synch. mode ac characteristics (address latch type, we controlled) 1. t wp (min)=70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t adv 7-nst bw 60 - ns t as(a) 0-nst wp 55 1) -ns t ah(a) 7-nst wlrl 1-clock t css(a) 10 - ns t as 0-ns t cw 60 - ns t dw 30 - ns t aw 60 - ns t dh 0-ns t adv
revision 1.0 january 2005 K1B6416B6C - 26 - u t ram (address latch type asynchronous write cycle - ub & lb controlled) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for word operation. a write ends at the earliest transition when cs goes or and we goes high. the t wp is measured from the beginning of write to the end of write. 2. t aw is measured from the address valid to the end of write. in this address latch type write timing, t wc is same as t aw. 3. t cw is measured from the cs going low to the end of write. 4. t bw is measured from the ub and lb going low to the end of write. 5. clock input does not have any affect to the write operation if the parameter twlrl is met. fig.20 timing waveform of wr ite cycle(address latch type) (mrs =v ih, oe =v ih , wait =high-z, ub & lb controlled) ub , lb we data in t bw t wp t dh t dw data valid adv address cs valid t as(a) t ah(a) t css(a) t cw data out high-z 12345678910111213 clk 0 t as read latency 5 high-z t wlrl 14 t aw t adv asynchronous write timing waveform in synchronous mode table 24. asynch. write in synch. mode ac characteristics (address latch type, ub & lb controlled) 1. t wp (min)=70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t adv 7-nst bw 60 - ns t as(a) 0-nst wp 55 1) -ns t ah(a) 7-nst wlrl 1-clock t css(a) 10 - ns t as 0-ns t cw 60 - ns t dw 30 - ns t aw 60 - ns t dh 0-ns
revision 1.0 january 2005 K1B6416B6C - 27 - u t ram (low adv type write cycle - we controlled) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest transition when cs goes high or we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs or we going high. 5. clock input does not have any affect to the write operation if the parameter twlrl is met. fig.21 timing wavefor m of write cycle(low adv type) (mrs =v ih, oe =v ih , wait =high-z, we controlled) asynchronous write timing waveform in synchronous mode address data valid ub , lb we data in t wc t cw t bw t wp t dh t dw t wr t aw t as cs adv data out high-z high-z 123456789 clk 0 read latency 5 10 11 12 13 14 t wlrl table 25. asynch. write in synch. mode ac characteristics (low adv type, we controlled) 1. t wp (min)=70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t wc 70 - ns t wlrl 1-clock t cw 60 - ns t as 0-ns t aw 60 - ns t wr 0-ns t bw 60 - ns t dw 30 - ns t wp 55 1) -nst dh 0-ns
revision 1.0 january 2005 K1B6416B6C - 28 - u t ram (low adv type write cycle - ub & lb controlled) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest transition when cs goes high or we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs or we going high. 5. clock input does not have any affect to the write operation if the parameter twlrl is met. fig.22 timing wavefor m of write cycle(low adv type) (mrs =v ih, oe =v ih , wait =high-z, ub & lb controlled) address data valid ub , lb we data in t wc t cw t bw t wp t dh t dw t wr t aw t as cs adv data out high-z clk read latency 5 123456789 0 10 11 12 13 14 t wlrl high-z asynchronous write timing waveform in synchronous mode table 26. asynch. write in synch. mode ac characteristics (low adv type, ub & lb controlled) 1. t wp (min)=70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t wc 70 - ns t wlrl 1-clock t cw 60 - ns t as 0-ns t aw 60 - ns t wr 0-ns t bw 60 - ns t dw 30 - ns t wp 55 1) -nst dh 0-ns
revision 1.0 january 2005 K1B6416B6C - 29 - u t ram fig.23 timing waveform of multiple write cycle(low adv type) (mrs =v ih, oe =v ih , wait =high-z, we controlled) asynchronous write timing waveform in synchronous mode address data valid ub , lb we data in t wc t cw t bw t wp t dh t dw t wr t aw t as cs adv data out high-z high-z 123456789 clk 0 10 11 12 13 t wc t as t wr data valid t dh t dw t whp t wp t cw t aw t bw (low adv type multiple write cycle) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest transition when cs goes high or we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs or we going high. 5. clock input does not have any affect to the asynchronous multiple write operation if t whp is shorter than (read latency - 1) clock duration. 6. t wp (min)=70ns for continuous wr ite operation over 50 times. 14 table 27. asynch. write in synch. mode ac characteristics (low adv type multiple write, we controlled) 1. t wp (min)=70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t wc 70 - ns t whp 5ns latency-1 clock - t cw 60 - ns t as 0-ns t aw 60 - ns t wr 0-ns t bw 60 - ns t dw 30 - ns t wp 55 1) -nst dh 0-ns
revision 1.0 january 2005 K1B6416B6C - 30 - u t ram table 28. synchronous ac characteristics (v cc =1.7~2.0v, t a =-40 to 85 c, maximum main clock fre- quency=66mhz) parameter list symbol speed units min max burst operation (common) clock cycle time t 15 200 ns burst cycle time t bc - 2500 ns address set-up time to adv falling(burst) t as(b) 0-ns address hold time from adv rising(burst) t ah(b) 7-ns adv setup time t advs 5-ns adv hold time t advh 7-ns cs setup time to clock rising(burst) t css(b) 5-ns burst end to new adv falling t beadv 7-ns burst stop to new adv falling t bsadv 12 - ns cs low hold time from clock t cslh 7-ns cs high pulse width t cshp 5-ns adv high pulse width t adhp 5-ns chip select to wait low t wl -10ns adv falling to wait low t awl -10ns clock to wait high t wh -12ns chip de-select to wait high-z t wz -12ns burst read operation ub , lb enable to end of latency clock t bel 1-clock output enable to end of latency clock t oel 1-clock ub , lb valid to low-z output t blz 5-ns output enable to low-z output t olz 5-ns latency clock rising edge to data output t cd -10ns output hold t oh 3-ns burst end clock to output high-z t hz -12ns chip de-select to output high-z t chz -12ns output disable to output high-z t ohz -12ns ub , lb disable to output high-z t bhz -12ns burst write operation we set-up time to command clock t wes 5-ns we hold time from command clock t weh 5-ns we high pulse width t whp 5-ns ub , lb set-up time to clock t bs 5-ns ub , lb hold time from clock t bh 5-ns byte masking set-up time to clock t bms 7-ns byte masking hold time from clock t bmh 7-ns data set-up time to clock t ds 5-ns data hold time from clock t dhc 3-ns ac operating conditions test conditions (test load and test input/output reference) input pulse level: 0.2 to v cc -0.2v input rising and falling time: 3ns input and output reference voltage: 0.5 x v cc output load: c l =30pf vtt=0.5 x vcc 50 ? dout 30pf z0=50 ? figure 24. ac output load circuit
revision 1.0 january 2005 K1B6416B6C - 31 - u t ram 123456789101112131415 adv address clk t advs t advh t as(b) t ah(b) t 0 t beadv don?t care valid valid burst command clock burst read end clock data out dq0 dq1 dq2 dq3 undefined data in d0 d1 d3 d0 d2 t beadv burst write end clock fig.25 timing waveform of basic burst operation [latency=5,burst length=4] (mrs =v ih ) synchronous burst operation timing waveform table 29. burst operation ac characteristics symbol speed units symbol speed units min max min max t 15 200 ns t as(b) 0-ns t bc - 2500 ns t ah(b) 7-ns t advs 5-nst css(b) 5-ns t advh 7-nst beadv 7-ns cs t css(b) t bc
revision 1.0 january 2005 K1B6416B6C - 32 - u t ram 123456789101112131415 adv address cs lb , ub data out oe clk dq0 dq1 dq2 dq3 undefined t cd valid latency 5 t hz valid t advs t advh t as(b) t ah(b) t css(b) t t oh don?t care fig.26 timing waveform of burst read cycle(1) [latency=5,burst length=4,wp=low enable] (we =v ih , mrs =v ih ) synchronous burst read timing waveform (synchronous burst read cycle - cs toggling consecutive burst read) 1. the new burst operation can be issued only after the previ ous burst operation is finished. for the new burst operation, tbea dv should be met. 2. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 4. burst cycle time(tbc) should not be over 2.5 s. wait t blz t bel t oel t olz high-z 0 t wh t wl t wz t chz t ohz t bhz t cshp t wl t wh - cs toggling consecutive burst read t beadv t bc table 30. burst read ac characteristics (cs toggling consecutive burst) symbol speed units symbol speed units min max min max t cshp 5-nst ohz -12ns t bel 1-clockt bhz -12ns t oel 1-clockt cd -10ns t blz 5-nst oh 3-ns t olz 5-nst wl -10ns t hz -12nst wh -12ns t chz -12nst wz -12ns
revision 1.0 january 2005 K1B6416B6C - 33 - u t ram 123456789101112131415 adv address cs lb , ub data out oe clk dq0 dq1 dq2 dq3 undefined t cd valid latency 5 t hz valid t advs t advh t as(b) t ah(b) t css(b) t t oh don?t care fig.27 timing waveform of burst read cycle(2) [latency=5,burst length=4,wp=low enable] (we =v ih , mrs =v ih ) synchronous burst read timing waveform (synchronous burst read cycle - cs low holding consecutive burst read) 1. the new burst operation can be issued only after the previ ous burst operation is finished. for the new burst operation, tbea dv should be met. 2. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 4. the consecutive multiple burst read operation with holding cs low is possible through issuing only new adv and address. 5. burst cycle time(tbc) should not be over 2.5 s. wait t blz t bel t oel t olz high-z 0 t wh t wl t awl t wh - cs low holding consecutive burst read t beadv t bc table 31. burst read ac characteristics (cs low holding consecutive burst) symbol speed units symbol speed units min max min max t bel 1-clockt cd -10ns t oel 1-clockt oh 3-ns t blz 5-nst wl -10ns t olz 5-nst awl -10ns t hz -12nst wh -12ns
revision 1.0 january 2005 K1B6416B6C - 34 - u t ram fig.28 timing waveform of burst read cycle(3) [latency=5,burst length=4,wp=low enable] (we =v ih , mrs =v ih ) adv address cs lb , ub data out oe clk dq0 dq1 dq2 undefined t cd valid latency 5 t advs t advh t as(b) t ah(b) t css(b) t t oh don?t care dq3 (synchronous burst read cycle - last data sustaining) 1. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 2. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 3. burst cycle time(tbc) should not be over 2.5 s. 1234567891011121314 synchronous burst read timing waveform t bel t oel t blz t olz wait high-z 0 t wl t wh t bc - last data sustaining table 32. burst read ac characteristics (last data sustaining) symbol speed units symbol speed units min max min max t bel 1-clockt cd -10ns t oel 1-clockt oh 3-ns t blz 5-nst wl -10ns t olz 5-nst wh -12ns
revision 1.0 january 2005 K1B6416B6C - 35 - u t ram 12345678910111213 adv address cs lb , ub data in we clk d0 d1 d2 d3 valid t advs t advh t as(b) t ah(b) t css(b) t t dhc fig.29 timing waveform of burst write cycle(1) [latency=5,burst length=4,wp=low enable] (oe =v ih , mrs =v ih ) synchronous burst write timing waveform (synchronous burst write cycle - cs toggling consecutive burst write) 1. the new burst operation can be issued only after the previ ous burst operation is finished. for the new burst operation, tbea dv should be met. 2. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 3. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 4. d2 is masked by ub and lb . 5. burst cycle time(tbc) should not be over 2.5 s. wait 0 t wes t weh t ds t dhc don?t care t bms t bmh latency 5 high-z t wl t wh valid t bs t bh d0 t whp t cshp t wz t wl latency 5 valid valid t wh - cs toggling consecutive burst write t beadv t bc table 33. burst write ac characteristics (cs toggling consecutive burst) symbol speed units symbol speed units min max min max t cshp 5-nst whp 5-ns t bs 5-nst ds 5-ns t bh 5-nst dhc 3-ns t bms 7-nst wl -10ns t bmh 7-nst wh -12ns t wes 5-nst wz -12ns t weh 5-ns
revision 1.0 january 2005 K1B6416B6C - 36 - u t ram 12345678910111213 adv address cs lb , ub data in we clk d0 d1 d2 d3 valid t advs t advh t as(b) t ah(b) t css(b) t t dhc fig.30 timing waveform of burst write cycle(2) [latency=5,burst length=4,wp=low enable] (oe =v ih , mrs =v ih ) synchronous burst write timing waveform (synchronous burst write cycle - cs low holding consecutive burst write) 1. the new burst operation can be issued only after the previ ous burst operation is finished. for the new burst operation, tbea dv should be met. 2. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 3. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 4. d2 is masked by ub and lb . 5. the consecutive multiple burst read operation with holding cs low is possible through issuing only new adv and address. 6. burst cycle time(tbc) should not be over 2.5 s. wait 0 t wes t weh t ds t dhc don?t care t bms t bmh latency 5 high-z t wl t wh valid t bs t bh d0 t whp t awl latency 5 valid valid t wh - cs low holding consecutive burst write t beadv t bc table 34. burst write ac characteristics (cs low holding consecutive burst) symbol speed units symbol speed units min max min max t bs 5-nst whp 5-ns t bh 5-nst ds 5-ns t bms 7-nst dhc 3-ns t bmh 7-nst wl -10ns t wes 5-nst awl -10ns t weh 5-nst wh -12ns
revision 1.0 january 2005 K1B6416B6C - 37 - u t ram fig.31 timing waveform of burst read stop by cs [latency=5,burst length=4,wp=low enable] (we =v ih , mrs =v ih ) 1234567891011121314 adv address cs lb , ub data oe clk dq0 undefined t cd don?t care valid latency 5 valid t advs t advh t as(b) t ah(b) t css(b) t t oh t chz synchronous burst read stop timing waveform wait t bel t oel t blz t olz t cslh (synchronous burst re ad stop timing) 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, tbsa dv should be met 2. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 4. the burst stop operation should not be repeated for over 2.5 s. t cshp high-z 0 high-z t wl t wh t wz t wl dq1 t bsadv table 35. burst read stop ac characteristics symbol speed units symbol speed units min max min max t bsadv 12 - ns t cd -10ns t cslh 7-nst oh 3-ns t cshp 5-nst chz -12ns t bel 1-clockt wl -10ns t oel 1-clockt wh -12ns t blz 5-nst wz -12ns t olz 5-ns
revision 1.0 january 2005 K1B6416B6C - 38 - u t ram fig.32 timing waveform of burst write stop by cs [latency=5,burst length=4,wp=low enable] (oe =v ih , mrs =v ih ) synchronous burst write stop timing waveform 12345678910111213 adv address cs lb , ub data in we clk d0 d1 valid t advs t advh t as(b) t ah(b) t css(b) t t dhc (synchronous burst wr ite stop timing) 1. the new burst operation can be issued only after the previous burst operation is finished. 2. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 4. the burst stop operation should not be repeated for over 2.5 s. wait 0 t wes t weh t ds valid d0 t cshp t cslh high-z high-z t wl t wh t wz t wl latency 5 latency 5 t wh d1 d2 don?t care t whp t bsadv table 36. burst write stop ac characteristics symbol speed units symbol speed units min max min max t bsadv 12 - ns t whp 5-ns t cslh 7-nst ds 5-ns t cshp 5-nst dhc 3-ns t bs 5-nst wl -10ns t bh 5-nst wh -12ns t wes 5-nst wz -12ns t weh 5-ns t bs t bh
revision 1.0 january 2005 K1B6416B6C - 39 - u t ram fig.33 timing waveform of burst read suspend cycle(1) [latency=5,burst length=4,wp=low enable] (we =v ih , mrs =v ih ) 123456 7891011 adv address cs lb , ub data out oe clk dq0 dq1 dq2 undefined t cd valid latency 5 t hz t advs t advh t as(b) t ah(b) t css(b) t don?t care fig.33 timing waveform of burst read suspend cycle(1) [latency=5,burst length=4,wp=low enable] (we =v ih , mrs =v ih ) synchronous burst read suspend timing waveform (synchronous burst read suspend cycle) 1. if clock input is halted during burst read operation, the data out will be suspended. during the burst read suspend period, oe high drives data out to high-z. if clock input is resumed, the suspended data will be out first. 2. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. during suspend period, oe high drives dq to high-z and oe low drives dq to low-z. if oe stays low during suspend period, the previous data will be sustained. 4. burst cycle time(tbc ) should not be over 2.5 s. wait t blz t bel t oel t olz high-z 0 t wh t wl dq1 t wz t ohz t olz dq3 high-z t bc table 37. burst read suspend ac characteristics symbol speed units symbol speed units min max min max t bel 1-clockt hz -12ns t oel 1-clockt ohz -12ns t blz 5-nst wl -10ns t olz 5-nst wh -12ns t cd -10nst wz -12ns t oh 3-ns t oh
revision 1.0 january 2005 K1B6416B6C - 40 - u t ram fig.34 synch. burst read to asynch. wr ite(address latch type) timing waveform 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv address cs lb , ub data out oe clk dq0 t cd valid latency 5 t hz valid t css(b) t t oh don?t care t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 21 dq1 dq3 dq2 we t css(a) data in t dh t dw data valid high-z high-z t as(a) t ah(a) [latency=5, burst length=4] (mrs =v ih ) t beadv (synchronous burst read cycle) 1. the new burst operation can be issued only after the previ ous burst operation is finished. for the new burst operation, tbea dv should be met. 2. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 4. burst cycle time(tbc) should not be over 2.5 s. (address latch type asynchronous write cycle - we controlled) 1. clock input does not have any affect to the write operation if we is driven to low before read late ncy-1 clock. read latency-1 clock in write timing is just a reference to we low going for proper write operation. t as read latency 5 0 t wp t wlrl t cw t aw t bw transition timing waveform between read and write t bc table 38. burst read to asynch. write( address latch type) ac characteristics symbol speed units symbol speed units min max min max t beadv 7-nst wlrl 1-clock wait high-z t wh t wl t wz high-z t adv
revision 1.0 january 2005 K1B6416B6C - 41 - u t ram 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv address cs lb , ub data out oe clk dq0 t cd valid latency 5 t hz t css(b) t t oh don?t care t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 21 dq1 dq2 we data in t dh t dw data valid high-z high-z t beadv t aw t cw t wp t bw fig.35 synch. burst read to asynch. write(low adv type) timing waveform [latency=5, burst length=4] (mrs =v ih ) t as t wr valid address (synchronous burst read cycle) 1. the new burst operation can be issued only after the previ ous burst operation is finished. for the new burst operation, tbea dv should be met. 2. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 4. burst cycle time(tbc) should not be over 2.5 s. (low adv type asynchronous write cycle - we controlled) 1. clock input does not have any affect to the write operation if we is driven to low before read latency-1 clock. read latency-1 clock in write timing is just a reference to we low going for proper write operation. read latency 5 transition timing waveform between read and write table 39. burst read to asynch. write(low adv type) ac characteristics symbol speed units symbol speed units min max min max t beadv 7-nst wlrl 1-clock t wlrl wait high-z t wh t wl t wz dq3 t bc high-z
revision 1.0 january 2005 K1B6416B6C - 42 - u t ram fig.36 asynch. write(address latch type ) to synch. burst read timing waveform [latency=5, burst length=4] (mrs =v ih ) 12345678910111213 1920 adv address cs lb , ub data out oe clk dq0 t cd valid latency 5 t hz valid t css(a) t t oh t bel t oel t advs t advh t as(a) t ah(a) 14 15 16 17 18 0 dq1 dq3 dq2 we t css(b) data in high-z t as(b) t ah(b) t wp t bw (synchronous burst read cycle) 1. the new burst operation can be issued only after the previ ous burst operation is finished. for the new burst operation, tbea dv should be met. 2. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 4. burst cycle time(tbc) should not be over 2.5 s. (address latch type asynchronous write cycle - we controlled) 1. clock input does not have any affect to the write operation if we is driven to low before read latency-1 clock. read latency-1 clock in write timing is just a reference to we low going for proper write operation. t as read latency 5 t dh t dw data valid don?t care don?t care t aw t cw transition timing waveform between read and write t adv t wlrl table 40. asynch. write(address latch type) to burst read ac characteristics symbol speed units symbol speed units min max min max t wlrl 1-clock wait high-z t wh t wl t wz t bc
revision 1.0 january 2005 K1B6416B6C - 43 - u t ram fig.37 asynch. write(low adv type) to synch. burst read timing waveform [latency=5, burst length=4] (mrs =v ih ) 12345678910111213 1920 adv address cs lb , ub data out oe clk dq0 t cd latency 5 t hz valid t t oh t bel t oel t advs t advh 14 15 16 17 18 0 dq1 dq3 dq2 we t css(b) data in high-z t as(b) t ah(b) t as t dh t dw data valid don?t care t aw t cw valid t wr t wp t bw t wc t adhp (synchronous burst read cycle) 1. the new burst operation can be issued only after the previ ous burst operation is finished. for the new burst operation, tbea dv should be met. 2. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 4. burst cycle time(tbc) should not be over 2.5 s. (low adv type asynchronous write cycle - we controlled) 1. clock input does not have any affect to the write operation if we is driven to low before read latency-1 clock. read latency-1 clock in write timing is just a reference to we low going for proper write operation. read latency 5 transition timing waveform between read and write table 41. asynch. write(low adv type) to burst read ac characteristics symbol speed units symbol speed units min max min max t wlrl 1-clockt adhp 5-ns t wlrl wait high-z t wh t wl t wz t bc
revision 1.0 january 2005 K1B6416B6C - 44 - u t ram high-z fig.38 synch. burst read to synch. burst write timing waveform [latency=5, burst length=4] (mrs =v ih ) transition timing waveform between read and write 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv address cs lb , ub data out oe clk dq0 t cd valid latency 5 t hz valid t css(b) t t oh don?t care t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 21 dq1 dq3 dq2 we t css(b) data in high-z high-z t beadv 0 t bc t as(b) t ah(b) d1 d3 d2 high-z d0 wait t wh t wl t wz latency 5 t bc t wes t weh t bs t bh t ds t dhc t wz t wl t wh table 42. burst read to burst write ac characteristics symbol speed units symbol speed units min max min max t beadv 7-ns (synchronous burst read & write cycle) 1. the new burst operation can be issued only after the previ ous burst operation is finished. for the new burst operation, tbea dv should be met. 2. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 4. burst cycle time(tbc) should not be over 2.5 s.
revision 1.0 january 2005 K1B6416B6C - 45 - u t ram high-z fig.39 synch. burst write to sy nch. burst read timing waveform [latency=5, burst length=4] (mrs =v ih ) transition timing waveform between read and write 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv address cs lb , ub data out oe clk t cd valid latency 5 t hz valid t css(b) t t oh don?t care t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 21 we t css(b) data in high-z t beadv 0 t bc t as(b) t ah(b) d1 d2 wait t wh t wl latency 5 t bc t wes t weh t bs t bh t ds t dhc t wz t wl t wh table 43. burst write to burst read ac characteristics symbol speed units symbol speed units min max min max t beadv 7-ns (synchronous burst read & write cycle) 1. the new burst operation can be issued only after the previ ous burst operation is finished. for the new burst operation, tbea dv should be met. 2. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 4. burst cycle time(tbc) should not be over 2.5 s. d3 d0 dq0 dq1 dq3 dq2 high-z
revision 1.0 january 2005 K1B6416B6C - 46 - u t ram c1/2 package dimension 654321 a b c d e f g h c b/2 b c1 b c bottom view top view d e2 e1 e c side view 0.55/typ. 0.35/typ. a y detail a min typ max a - 0.75 - b 5.90 6.00 6.10 b1 - 3.75 - c 7.90 8.00 8.10 c1 - 5.25 - d 0.40 0.45 0.50 e - 0.90 1.00 e1 - 0.55 - e2 0.30 0.35 0.40 y- -0.10 b1 #a1 notes. 1. bump counts: 54(9 row x 6 column) 2. bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. all tolerence are 0.050 unless specified beside figures. 4. typ : typical 5. y is coplanarity: 0.10(max) unit: millimeters 54 ball fine pitch bga(0.75mm ball pitch) j

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